1. Field of the Invention
The present invention relates to a single error correction circuit for a system memory.
2. Description of Prior Art
Memory errors are tending to become more and more frequent as the total system memory is growing and the geometry of individual memory cells is shrinking, making them more susceptible to "soft" and "hard" errors.
To avoid a system crash or a loss of data integrity memory errors have to be recovered during system operation.
The identification and the correction of errors present on information readout from the memory is possible by means of redundancy codes among which the most commonly used, the so-called SEC-DED (Single Error Correction-Double Error Detection), provide detection and correction of single bit errors in the readout data and detection, but not correction, of double errors on the readout data.
The use of redundancy codes requres that, in storing a binary coded information, the error correcting code associated with the information must be generated and then stored in the memory along with the information. Likewise it is necessary, before using information readout from the memory, to process it by generating the related code and comparing it with the one already stored and readout with the information. From this comparison an error condition may result which, through a correction network, leads, if necessary, to the correction of the read out information.
These operations of correction code generation, correction code regeneration on readout, comparison and correction, if necessary, are performed by means of logical circuits which have a certain, non negligible intervention time.
In the case of error code generation during a write operation in memory, the generation time and the time required for memory addressing may overlap, consequently no delay is added.
However, in the case of error code regeneration and comparison during a read operation the necessary functions can be performed only after the reading has been completed, whereupon the validation process imposes a certain delay time on memory readout operations.
This delay may greatly hamper memory performance as it is a non negligible percentage of the readout time.
Referring to error detection/correction systems used in the prior art and described in a lot of patents, as for instance U.S. Pat. Nos. 4,319,356 and 4,380,812, the circuits of such systems which intervene during a memory read operation substantially comprise a syndrome bit generator receiving in input the information and the related error correcting code readout from memory, a syndrome decoder receiving in input the syndrome bits and a correction circuit receiving in input the information readout from the memory and the signals on the outputs of the syndrome decoder, each of said signals being associated to a prefixed bit of the readout information to indicate the correctness or incorrectness of such bit.
The validation delay time .DELTA.T.sub.V introduced by the above circuits may be expressed as follows: EQU .DELTA.T.sub.V =.DELTA.T.sub.SG +.DELTA.T.sub.SD +.DELTA.T.sub.CC
where:
.DELTA.T.sub.SG is the propagation delay time of the syndrome generator, PA1 .DELTA.T.sub.SD is the propagation delay time of the syndrome decoder PA1 .DELTA.T.sub.CC is the propagation delay time of the correction circuit.
It is to be noted that in the expression of .DELTA.T.sub.V the terms .DELTA.T.sub.SG and .DELTA.T.sub.CC generally predominate over .DELTA.T.sub.SD because both the syndrome generator and the correction circuit are implemented by means of EX-OR logical gates which have a propagation delay much higher than the one of other logical gates.